This invention relates, in general, to semiconductor devices, and more particularly to a method of fabricating a semiconductor device having internal current limit and overvoltage protection.
Because of the environments in which they reside and various other factors, many semiconductor devices are subject to overvoltage and large current fluctuations. This is especially true in power discrete devices including those used in integrated circuits. For instance, it is extremely difficult to operate a bipolar power device under maximum power conditions, yet avoid destruction under certain unpredictable voltage and current conditions.
Many methods and structures have been developed to protect semiconductor devices from destruction due to the voltage and current conditions of their environments. However, typical protective structures are external to the intrinsic device. One prior art method of device protection includes the addition of internal or external zener diodes to clamp the emitter-base or collector-emitter junction voltage. When the voltage exceeds the zener voltage, the zener diodes turn on, thereby limiting current. An obvious problem with this method is that the number of zener diodes employed internally depends upon the voltage which the primary transistor is to be turned off. When a high voltage transistor is employed, an excessive number of zener diodes must also be employed. This dissipates power, increases cost, and increases the amount of chip area required.
Another protective method includes the incorporation of emitter ballast resistors to improve the uniformity of current distribution in a device and increase the maximum limit of power dissipation. Although this is somewhat successful, it still requires the addition of external devices which require increased amounts of chip area.
In view of the above, it would be highly desirable to have a method of internally limiting current and providing overvoltage protection in a semiconductor device that employs no additional devices, does not dissipate power, requires no additional chip area, and wherein the pinch-off voltage may be adjusted.